In machine vision components, especially cameras, the standard GigE Vision^® is now established. This standard specifies an UDP based messaging protocol to transfer data, messages and events. This could be the image data of a camera that are sent to a PC and command or configuration data that are sent to a camera device.

Sensor to Image offers a set of FPGA IP cores to fasten up design of GigE Vision^® compliant machine vision devices, e.g. cameras , but also receiving components like GigE framegrabbers.

At the moment the Altera FPGA families Cyclone III, Cyclone IV, Arria GX, Arria II GX, and Stratix IV are supported.

The design is prepared for 10 Gigabit and LinkAggregation and will support it as cost effective components are available (10GBit needs at least 8 3.125GBit FPGA transceivers).

To get an easy access to this design solution, Sensor to Image provides an HSMC Addon Board, which could be used on standard Altera eval boards to test sending and receiving applications.

Reference designs exist for following boards:

• Cyclone® III Starter Kit
• Cyclone® IV Industrial Networking Kit, DEVICE and HOST, 1GBit. For this hardware we have a free DEVICE reference design, which you can register for here.
• Cyclone® V M-Pression Beryll, DEVICE, 1GBit
• Arria® V Starter Kit, DEVICE, 1GBit

You can find the data sheet here, and for further information press here...