GigE Vision FPGA Core Xilinx

GigE Core Evaluation Board In machine vision components, especially cameras, the standard GigE Vision® is now established. This standard specifies an UDP based messaging protocol to transfer data, messages and events. This could be the image data of a camera that are sent to a PC and command or configuration data that are sent to a camera device.

Sensor to Image offers a set of FPGA IP cores to fasten up design of GigE Vision® compliant machine vision devices, e.g. cameras , but also receiving components like GigE framegrabbers.

At the moment as 1/2/10GBit DEVICE=sender=camera and 1/10GBit HOST=receiver=frame grabber the Xilinx FPGA families Spartan3/6, Virtex5/6, Artix, Kintex and ZYNQ are supported.

To get an easy access to this design solution, Sensor to Image provides a Spartan3E based evaluation-kit for sending and receiving applications. In addition following Xilinx boards are supported:

  • Spartan3ADSP-1800 DEVICE and HOST, 1GBit on S2I video converter hardware
  • Spartan6®, SP605, DEVICE and HOST, 1GBit. For this hardware we have a free DEVICE reference design, which you can register for here.
  • Virtex6®, ML605, DEVICE and HOST, 1 and 10GBit
  • Artix7®, AC701, DEVICE and HOST, 1GBit. For this hardware we have a free DEVICE reference design, which you can register for here.
  • Kintex®, KC705, DEVICE and HOST, 1/5/10 GBit, SFP+
  • ZYNQ®, ZC702, DEVICE and HOST, 1GBit
  • ZYNQ®, ZC706, DEVICE and HOST, 1/5/10 GBit, SFP+

You can find the data sheet here, and for further information press here...