In machine vision components, especially cameras, the standard CoaXPress^® has almost established. This standard specifies an high speed protocol and direct interface to data acquisition devices. The protocol supports transfer of data, messages and events. This could be the image data of a camera that are sent to a PC frame grabber and command or configuration data that are sent to a camera device. All communication and device power is transmitted over a single 75 Ohm coaxial cable, which is widely used for PAL/NTSC cameras at transfer speeds of up to 6.125GBit/cable.

Sensor to Image offers a set of FPGA IP cores to fasten up design of CoaXPress^® compliant machine vision devices, e.g. cameras , but also receiving components like GigE framegrabbers.

At the moment the Altera FPGA families Cyclone® III, Cyclone® IV are supported.

The design on Cyclone FPGA works with an external SERDES at 1.25GBit/200m and 2.5Gbit/100m cable length. The design is prepared for 6.125GBit/50m cable length, where the SERDES has to be an FPGA internal of the ARIA® and STRATIX® families.

To get an easy access to this design solution, Sensor to Image provides an HSMC Addon Board, which could be used on standard ALTERA evaluation boards to test sending and receiving applications.

Reference designs exist for following boards:

• Cyclone® IV Industrial Networking Kit (TX device only)
• Arria® V Starter Kit, DEVICE and HOST

You can find the data sheet here, and for further information press here...